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S3C8478/C8475/P8475
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RC PRODUCT FAMILY
Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have an external interface that provides access to external memory and other peripheral devices. A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to one interrupt level at a time.
S3C8478/C8475 MICROCONTROLLER
The S3C8478/C8475 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter, UART, PWM application field. Its powerful SAM87RC CPU architecture includes. The internal register file is logically expanded to increase the on-chip register space. The S3C8478/C8475 has 8/16K bytes of on-chip program ROM. Following Samsung's modular design approach, the following peripherals are integrated with the SAM87RC core: -- Large number of programmable I/O ports (42 SDIP: 34 pins, 44 QFP: 36 pins) -- One asynchronous UART module -- Analog-to-digital converter with eight input channels and 10-bit resolution -- One 8-bit basic timer for watchdog function -- One 8-bit timer/counter with three operating modes (Timer 0) -- One general-purpose 16-bit timer/counters with three operating modes (Timer 1) The S3C8478/C8475 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, PWM, capture, and UART. It is available in a 42-pin SDIP or 44-pin QFP package.
OTP
The S3C8475 is an OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. The S3C8475 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM. The S3C8475 is comparable to the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C8478/C8475/P8475
FEATURES
CPU * SAM87RC CPU core UART * * Memory * * 272-byte general purpose register area 8/16K-byte internal program memory A/D Converter * Instruction Set * * 79 instructions IDLE and STOP instructions added for power-down modes * * Eight analog input pins 10-bit conversion resolution 20 s conversion time (10 MHz CPU clock) One UART module Full duplex serial I/O interface with three UART modes
Buzzer Frequency Output * 200 Hz to 20 kHz signal can be generated
Instruction Execution Time * 333 ns at 12 MHz fOSC (minimum) Oscillator Frequency * Interrupts * * * 14 interrupt sources and 14 vectors Eight interrupt levels Fast interrupt processing Operating Temperature Range * - 40C to + 85C * 1 MHz to 12 MHz external crystal oscillator Maximum 12 MHz CPU clock
General I/O * * * Five I/O ports (total 36 pins) Four bit-programmable ports Two n-channel open-drain output port
Operating Voltage Range * 1.8 V to 5.5 V
Package Types * 42-pin SDIP, 44-pin QFP
Timer/Counters * * * One 8-bit basic timer for watchdog function One 8-bit timer/counter with three operating modes (timer 0) One 16-bit general-purpose timer/counters with three operation modes (timer 1)
1-2
S3C8478/C8475/P8475
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7
P1.0-P1.5 T0, T1CK, T1, BUZ, RxD, TxD
Basic Timer
Port 0
Port 1
XIN XOUT T0(CAP) T0(PWM)
OSC
Timer 0
Port I/O and Interrupt Control
Port 2
P2.0-P2.7 INT0-INT7
T1(CAP) T1(PWM)
Timer 1 Port 3 P3.0-P3.7 ADC0-ADC7
SAM87RC CPU
ADC0-ADC7 ADC
P1.4/RxD P1.5/TxD
UART P4.0-P4.3
P1.3/BUZ
BUZ
8/16-Kbyte ROM
272-byte Register File
Port 4 P4.4-P4.5
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8478/C8475/P8475
PIN ASSIGNMENTS
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P4.3 P4.2 VDD VSS XOUT XIN TEST P4.1 P4.0 RESET P2.0/INT0 P2.1/INT1 P2.2/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
S3C8478 S3C8475
42-SDIP (Top-View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P1.0/T0 (CAP/PWM) P1.1/T1CK P1.2/T1 (CAP/PWM) P1.3/BUZ P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVREF P2.7/INT7 P2.6/INT6 P2.5/INT5 P2.4/INT4 P2.3/INT3
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
1-4
S3C8478/C8475/P8475
PRODUCT OVERVIEW
44 43 42 41 40 39 38 37 36 35 34
P4.4 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ
P0.1 P0.0 P4.3 P4.2 VDD VSS XOUT XIN TEST P4.1 P4.0
1 2 3 4 5 6 7 8 9 10 11
S3C8478 S3C8475
44-QFP (Top-View)
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P4.5 AVREF
1-5
PRODUCT OVERVIEW
S3C8478/C8475/P8475
Table 1-1. S3C8478/C8475 Pin Descriptions Pin Name P0.0-P0.7 Pin Type I/O Pin Description Nibble-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assignable by software. Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pin can also by used as alternative function (T0, T1CK, T1, BUZ, RxD, TxD) Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 2 pins can also be used as external interrupt. Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter by software. Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain output. Pull-up resistors are assingable by software. Push-pull output only Crystal or ceramic oscillator signal for system clock. System reset signal input pin. Test signal input pin (for factory use only; muse be connected to VSS) A/D converter reference voltage input and ground Voltage input pin and ground Timer 0 capture input or PWM output pin Timer 1 external clock input pin Timer 1 capture input or PWM output pin 200Hz-20kHz frequency output for buzzer sound UART receive and transmit input or output UART transmit output External interrupt input A/D converter input Circuit Number E Pin Number 8-1 (2-1, 43-38) 42-37 (37-32) Share Pins -
P1.0-P1.5
I/O
D
T0, T1CK, T1, BUZ, RxD, TxD INT0INT7
P2.0-P2.7
I/O
D
19-26 (13-20)
P3.0-P3.7
I/O
F
29-36 (24-31)
ADC0ADC7
P4.0-P4.3
I/O
E
17-16, 10-9 (11-10, 4-3) (44, 21) 14, 13 (8, 7) 18 (12) 15 (9) 27, 28 (22, 23) 11, 12 (5, 6) 42 (37) 41 (36) 40 (35) 39 (34) 38 (33) 37 (32) 19-26 (13-20) 29-36 (24-31)
-
P4.4-P4.5 XIN, XOUT RESET TEST AVREF, AVSS VDD, VSS T0 T1CK T1 BUZ RxD TxD INT0-INT7 ADC0ADC7
O - I I - - I/O I I/O O I/O O I I
C - B - - - D D D D D D E F
- - - - - - P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P2.0-P2.7 P3.0-P3.7
NOTE: Pin numbers shown in parentheses "( )" are for the 44-pin QFP package.
1-6
S3C8478/C8475/P8475
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-Channel In N-Channel
Data
P-Channel Out
Output DIsable
N-Channel
Figure 1-4. Pin Circuit Type A
Figure 1-6. Pin Circuit Type C
VDD VDD Pull-Up Resistor In
Pull-up Enable Data Output DIsable Circuit Type C In/Out
Schmitt Trigger Data
Figure 1-5. Pin Circuit Type B
Figure 1-7. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C8478/C8475/P8475
VDD PNE 47 K Pull-up Enable P-CH Data Output DIsable N-CH In/Out
VDD
Schmitt Trigger
Figure 1-8. Pin Circuit Type E
VDD
Pull-up Enable Data Output DIsable Data Circuit Type C In/Out
TO ADC
Figure 1-9. Pin Circuit Type F
1-8
S3C8478/C8475/P8475
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this chapter, S3C8478/C8475 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Input/output capacitance -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Data retention supply voltage in stop mode -- UART timing characteristics in mode 0 -- A/D converter electrical characteristics
14-1
ELECTRICAL DATA
Table
A
1. Absolute Maximum Ratings
= 25 C) Parameter Symbol VDD VI VO I OH I OL All ports All output ports One I/O pin active All I/O pins active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 + 200 - 40 to + 85 - 65 to + 150
C C
Unit V V V mA
Supply Voltage Input Voltage Output Voltage Output Current High
Output Current Low
One I/O pin active Total pin current for ports 1, 2, and 3 Total pin current for ports 0 and 4
mA
Operating Temperature Storage Temperature
TA TSTG
- -
14-2
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH3 Input Low Voltage VIL1 VIL3 Output High Voltage Output Low Voltage VOL1 VOH Test Conditions Ports 0, 1, 2, 3 ,4 and RESET XIN, and XOUT Ports 0, 1, 2, 3, 4 and RESET XIN and XOUT IOH = - 1 mA Ports 0, 1, 2, 3, 4 IOL = 15 mA Port 0, and 4 VOL2 Input High Leakage Current ILIH1 ILIH2 Input Low Leakage Current ILIL1 ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH ILOL RP1 RP1 Supply Current IDD1 IOL = 4 mA Ports 1, 2, and 3 All input pins except VIN = VDD ILIH2 and RESET XIN, and XOUT VIN = VDD - - All input pins except VIN = 0 V ILIL2 XIN, and XOUT All output pins All output pins VIN = 0 V VOUT = VDD VOUT = 0 V - - 30 100 - - - 47 200 10 1.1 - 4 0.6 - 0.1 0.1 - - 1 20 -1 - 20 2 -2 70 350 20 3 8 1.5 5 3 uA mA uA uA K uA uA VDD = 4.5 to 5.5 V 0.4 2.0 V VDD = 4.5 to 5.5 V - 0.4 2.0 V VDD = 2.7 to 5.5 V Min 0.8 VDD VDD-0.1 VDD = 2.7 to 5.5 V - - 0.2 VDD 0.1 VDD = 4.5 to 5.5 V VDD-1.0 - - V Typ - Max VDD Unit V
VIN = 0 V, Ports 0-4 VDD = 5 V RESET RUM mode 12 MHz CPU clock 3 MHz CPU clock Idle mode 12 MHz CPU clock 3 MHz CPU clock Stop mode VDD = 5 V VDD = 4.5 to 5.5 V VDD = 1.8 to 2.2 V VDD = 4.5 to 5.5 V VDD = 1.8 to 2.2 V VDD = 4.5 to 5.5 V VDD = 1.8 to 2.2 V
IDD2
IDD3
14-3
ELECTRICAL DATA
S3C8478/C8475/P8475
Table 14-3. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Interrupt Input High, Low Width RESET Input Low Width Symbol tINTH, tINTL tRSL Conditions Ports 2 VDD = 5 V 10 % Input VDD = 5 V 10 % Min - - Typ 200 1 Max - - Unit ns s
tINTL tRST 0.8 VDD 0.2 VDD
tINTH
Figure 14-1. Input Timing Measurement Points
14-4
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-4. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Main Crystal or Ceramic
XIN XOUT
Clock Circuit
Test Condition VDD = 4.5 V to 5.5 V VDD = 2.7 V to 4.5 V VDD = 1.8 V to 2.7 V
Min 1
Typ -
Max 12 8 3
Unit MHz
C1
C2
External Clock (Main System)
XIN XOUT
VDD = 4.5 V to 5.5 V VDD = 2.7 V to 4.5 V VDD = 1.8 V to 2.7 V
1
-
12 8 3
MHz
14-5
ELECTRICAL DATA
S3C8478/C8475/P8475
CPU Clock 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 2 3 4 5
Main Oscillator Frequency (Divided by 4)
6
7
1.8 V 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-2. Operating Voltage Range
Table 14-5. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Main Crystal Main Ceramic External Clock (Main System) Oscillator Stabilization Wait Time f OSC > 1.0 kHz; Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) tWAIT when released by an interrupt (2) Test Condition Min - - 25 - - Typ - - - 216/fOSC
-
Max 20 10 500 - -
Unit ms ms ns ms ms
NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON.
14-6
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-6. UART Timing Characteristics in Mode 0 (10 MHz) (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V, Load capacitance = 80 pF) Parameter Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge Serial port clock High, Low level width Symbol tSCK tS1 tS2 tH1 tH2 tHIGH, tLOW Min 500 300 - tCPU - 50 0 200 Typ tCPU x 6 tCPU x 5 - tCPU - tCPU x 3 Max 700 - 300 - - 400 Unit ns
NOTES: 1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency. 2. The unit tCPU means one CPU clock period.
tHIGH
0.8 V DD 0.2 V DD t LOW t SCK
Figure 14-3. Waveform for UART Timing Characteristics
14-7
S3C8478/C8475/P8475
tSCK
SHIFT CLOCK
tH1 tS1
DATA OUT D0 D1 D2 D3 D4 D5 D6
D7
tS2
DATA IN
VALID VALID
t H2
VALID VALID VALID VALID
VALID
VALID
NOTE:
The symbols shown in this diagram are defined as follows:
tSCK tS1 tS2 tH1 tH2
ELECTRICAL DATA
Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge
Figure 14-4. A.C. Timing Waveform for the UART Module
14-8
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-7. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Data Retention Supply Voltage Data Retention Supply Current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 1.8 V Min 1.8 - Typ - 0.1 Max 5.5 5 Unit V A
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
RESET occurs
Stop Mode Data Retention Mode
Oscillation Stabilzation Time
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction RESET tWAIT
Normal Operating Mode
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 14-5. Stop Mode Release Timing When Initiated by a Reset
VOUT VDD A = 0.2 VDD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS
A
B
C
D
VIN
Figure 14-6. Schmitt Trigger Input Characteristics
14-9
ELECTRICAL DATA
S3C8478/C8475/P8475
Table 14-8. A/D Converter Electrical Characteristics (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance ADC reference voltage ADC reference ground Analog input current Analog block current (2) Symbol - ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC f OSC = 10 MHz (3) - - - - AVCC = VCC = 5 V AVCC = VCC = 5 V AVCC = VCC = 3 V AVCC = VCC = 5 V power down mode 20 AVSS 2 2.5 VSS - - Test Conditions VDD = 5.12 V CPU clock = 8 MHz AVREF = 5.12 V AVSS = 0 V Min - Typ - - - 1 1 - - - - - - 1 0.5 100 Max 3 2 1 3 2 - AVREF - VDD VSS + 0.3 10 3 1.5 500 nA s V M V V A mA Unit LSB
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock.
14-10
S3C8478/C8475/P8475
ELECTRICAL DATA
Digital Output 11 1111 1111 11 1111 1110 11 1111 1101
. . . . .
00 0000 0010 00 0000 0001 00 0000 0000 AVSS VEOB V2 V(K-1) V(K) Analog Input VEOT AVREF
1LSB = (VEOT-VEOB)/1022 DLE(K) = {(V(K)-V(K-1))-1LSB}/1LSB ILE(K) = {V(K)-(1LSB x K + VEOB)}/1LSB DLE = MAX{DLE(K)} ILE = MAX{ILE(K)}
Figure 14-7. Definition of DLE and ILE
14-11
S3C8478/C8475/P8475
MECHANICAL DATA
15
OVERVIEW
-- Pad diagram
#42
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
#22
0-15
14.00 0.2
#1
#21
39.10 0.2
3.50 0.2
39.50 MAX
0.50 0.1 (1.77) 1.00 0.1 1.778
NOTE:
Dimensions are in millimeters.
Figure 15-1. 42-SDIP-600 Package Dimensions
0.51 MIN
3.30 0.3
5.08 MAX
0.2
5
+0 - 0 .1 .05
42-SDIP-600
15.24
15-1
MECHANICAL DATA
S3C8478/C8475/P8475
13.20 0.3 0-8 10.00 0.2 0.15
+ 0.10 - 0.05
13.20 0.3
10.00 0.2
44-QFP-1010
0.80 0.20 #1 0.80
+ 0.10
0.10 MAX
#44
0.35 - 0.05 (1.00)
0.05 MIN 2.05 0.10 2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 15-2. 44-QFP-1010 Package Dimensions
15-2
S3C8478/C8475/P8475
S3P8475 OTP
16
OVERVIEW
S3P8475 OTP
The S3P8475 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8475 is fully compatible with the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P8475 is ideal as an evaluation chip for the S3C8478/C8475.
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 SDAT/P4.3 SCLK/P4.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.0 RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
S3P8475
(42-SDIP) Top-View
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVREF P2.7/INT7 P2.6/INT6 P2.5/INT5 P2.4/INT4 P2.3/INT3
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P8475 Pin Assignments (42-SDIP Package)
16-1
S3P8475 OTP
S3C8478/C8475/P8475
44 43 42 41 40 39 38 37 36 35 34
P4.4 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0/T0(CAP/PWM) P1.1/T1CK P1.2/T1(CAP/PWM) P1.3/BUZ
P0.1 P0.0 SDAT/P4.3 SCLK/P4.2 VDD/VDD VSS/VSS XOUT XIN VPP/TEST P4.1 P4.0
1 2 3 4 5 6 7 8 9 10 11
S3P8475
(44-QFP) Top-View
33 32 31 30 29 28 27 26 25 24 23
P1.4/RxD P1.5/TxD P3.7/ADC7 P3.6/ADC6 P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS
NOTE:
Figure 16-2. S3P8475 Pin Assignments (44-QFP Package)
16-2
RESET/RESET RESET P2.0/INT0 P2.1/INT1 P2.2/INT2 P2.3/INT3 P2.4/INT4 P2.5/INT5 P2.6/INT6 P2.7/INT7 P4.5 AVREF The bolds indicate an OTP pin name.
12 13 14 15 16 17 18 19 20 21 22
S3C8478/C8475/P8475
S3P8475 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P4.3 Pin Name SDAT Pin No. 9(3) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is aplied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P4.2 TEST
SCLK VPP
10(4) 14(16)
I I
RESET VDD/VSS
RESET VDD/VSS
18(12) 11(5)/12(6)
I -
NOTE: ( ) means 44 QFP package.
Table 16-2. Comparison of S3C8475 and S3C8478/C8475 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 1.8 V to 5.5 V VDD = 5 V, VPP (EA) = 12.5 V 42 SDIP/44 QFP User Program 1 time 42 SDIP/44 QFP Programmed at the factory S3C8475 16-Kbyte EPROM S3C8478/C8475 8/16-Kbyte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3C8475, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 ADDRESS (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection MODE
NOTE: "0" means Low level; "1" means High level.
16-3

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